The shift from analog signal processing (ASP) to digital signal processing (DSP) lies behind the tremendous development of information processing systems that are used today. For example, DSP has enabled the fast growth of mobile communication systems and has opened up for new sophisticated medical aids, just to mention a couple of important applications. The foremost advantages of DSP over ASP are its robustness and that it can perform functions with arbitrary precision. The trend during the past decades has therefore been to use as little ASP as possible and to replace analog functions with the corresponding digital functions. The real world is however analog by nature which means that the need for ASP cannot be eliminated completely. In particular, it will always be necessary to use analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), whenever there is a desire to communicate with other human beings or machines. The present document is concerned with ADCs.
During the past decades, the research and development of ADCs have been quite intensive, both in academia and industry. Nevertheless, it is foreseen that ADCs will remain key components as well as bottlenecks in many contexts of tomorrow. For example, it can be envisaged that an ADC capable of a sampling rate of more than 100 MHz and 17 bits resolution is required in fourth-generation communication systems. This is beyond the state-of-the art ADCs which can manage only some 13-14 effective bits of resolution at this rate. It is therefore vital to continue to invent new ADCs principles, techniques, and architectures to improve the performance of the AD conversion.
ADCs can be categorized into different classes depending on the underlying principle of the conversion process. This paper concerns a principle referred to as time-interleaved ADCs which utilizes interleaving of multiple ADCs to increase the effective sampling rate.
A time-interleaved ADC array is commonly used when a single ADC is not capable of meeting the needed sampling rate while providing desired conversion resolution. A time-interleaved ADC (TI-ADC) array comprises a plurality of ADCs arranged in parallel fashion with a signal to be converted being provided to each ADC of the plurality of ADCs in the array. Each ADC is responsible for converting only a portion of the signal and can therefore perform the conversion at a slower rate. For example, if a TI-ADC array has an integer number of M ADCs arranged in parallel fashion, then each of the M number of ADCs is only required to convert the signal at 1/M-th of the desired sampling rate.
Rather than having a single high conversion rate, high resolution ADC that is capable of converting an analog signal at a sampling rate, fs, the TI-ADC array makes use of M ADCs arranged in parallel configuration. Each of the ADCs has a sampling rate of fs/M. Therefore the sampling rate of the ADCs can be significantly lower than the sampling rate, fs of the overall TI-ADC array. With the lower sampling rate, cheaper ADCs can be used, ADCs with a higher conversion resolution can be used and the sampling rate of the TI-ADC array can be pushed higher.
Each of the M ADCs needs to operate at a sampling rate of fs/M. Once every M·T seconds, wherein T is an inverse of the sampling frequency, fs, the demultiplexer couples an input of an ADC to the input signal. Each signal path containing an ADC can be referred to as a channel.
A multiplexer can be used to recombine outputs from the M ADCs back to a single output stream, a digital signal stream made up of digitized samples of the output signal. The output signal from the TI-ADC comprises a sequence of digitized samples, one every T seconds, with a number of bits in each digitized sample being determined by a conversion resolution of the M ADCs. The multiplexer changes a coupling between an output of one of the M ADCs to the output signal from the TI-ADC at a frequency that is substantially equal to the sampling rate.
By use of an M-channel time-interleaved ADC, the effective sampling rate is increased by a factor of M, but the resolution of the individual channel converters is unfortunately not maintained in the overall converter due to channel mismatch errors. To restore the resolution, it is therefore necessary to compensate for these errors. Up to a certain resolution, it is enough to compensate for static gain, and linear-phase (time-skew) errors (There also exist static offset mismatch errors but they are independent of signal transfer characteristics and are easy to compensate for). Several techniques for this purpose have been proposed over the last decades. However, to reach a very high resolution (more than some 12 bits) for high-speed conversion (above some 100 Megasamples/s), account has to be taken into that the different channel ADCs are essentially lowpass filters with different frequency responses, thus with different phase responses as well as magnitude responses. To reach a very high resolution, it is necessary to suppress these frequency response mismatch errors, not only the static gain and linear-phase parts which is enough for a first-order approximation of the channel frequency responses. Up to now, only a few papers have addressed the more general problem. Some of these papers, herein referred to as general prior art, and in their entirety incorporated into this description, are:    [1] T. Tsai, P. J. Hurst, and S. H. Lewis, “Bandwidth mismatch and its correction in time-interleaved analog-to-digital converters,”, IEEE Trans. Circuits Syst. II, vol. 53, no. 10, pp. 1133-1137, October 2006.    [2] M. Seo, M. J. W. Rodwell, and U. Madhow, “Comprehensive digital correction of mismatch errors for a 400-Msamples/s 80-db SFDR time-interleaved analog-to-digital converter,”, IEEE Trans. Microwave Theory Techniques, vol. 53, no. 3, pp. 1072-1082, March 2005.    [3] S. Mendel and C. Vogel, “A compensation method for magnitude response mismatches in two-channel time-interleaved analog-to-digital converters,” in Proc. IEEE Int. Conf. Electronics, Circuits, Syst., Nice, France, December 2006.    [4] S. Mendel and C. Vogel, “On the compensation of magnitude response mismatches in M-channel time-interleaved ADCs.”, in Proc. IEEE Int. Symp. Circuits, Syst., New Orleans, USA, 2007 May.
The references [1]-[4] disclose use of compensation filters connected to the output of the channels of the TI-ADC. In reference [1], M synthesis filters are designed separately by use of a technique that approximates the desired filter frequency responses utilizing windowing techniques. Such design is known to result in suboptimum filters as they are based on truncation and weighting of ideal impulse responses instead of optimization. Reference [2] discloses a design with optimum filters based on least squares, wherein the filters are designed in terms of M synthesis filters, which are designed simultaneously by inverting one matrix of size M times the filter impulse response length.
A somewhat different compensation technique, that also utilizes separately designed filters, is disclosed in references [3] and [4], but the technique presented therein requires additional cosine and sine modulators which increases the implementation cost for the compensation system. Furthermore, references [3] and [4] only treat magnitude response mismatch errors of frequency response mismatch errors.
Other documents relating to methods for performing compensation of mismatch errors in time-interleaved ADC arrays are, e.g. US 2006/0279445 and US 2007/0069937. The method in the former of these cited documents suggests adjusting a delay imparted on a sampling clock by an adjustable delay in each channel. The second of the cited documents suggests the use of a reference ADC, by means of which a timing error is generated for use as a change of the phase of the sampling clock provided to the ADC and to estimate gain and DC offset errors for modifying values of reference voltages applied to the converter. The disclosures of said patent documents thus present solutions to problems as discussed in paragraph [0009].